This invention relates to a semiconductor memory device comprised of a plurality of memory cells, each cell having one transistor and one capacitor.
FIG. 1 shows a circuit diagram of a conventional memory cell 1 of a dynamic random access memory (DRAM). including an MOS transistor 2 and a capacitor 3. The gate electrode of the transistor is connected to a word line 5, the source electrode is connected to a bit line 4, and the capacitor is connected between the drain electrode and a fixed potential node.
FIG. 2 shows a simplified horizontal or plan view of a memory cell portion of a conventional DRAM. One end of each of a pair of bit lines 4a, 4b is connected to a sense amplifier. The bit line in each column is connected to the source electrode of the transistor 2 in each column through a contact hole 7. The word lines 5 are disposed perpendicular to the bit lines 4a, 4b. Part of each word line in each column is connected to the gate electrode of a transistor 2. An isolating region 6 surrounds and isolates each memory cell 1 from adjacent cells. The isolating region 6 may be a thick insulating material formed on a major surface of a semiconductor substrate, a deep trench formed in a major surface of the substrate, or an impurity region of the same conductivity type as the substrate and having a higher impurity concentration than that of the substrate.
The capacitor 3 in each memory cell includes a cell plate, a thin insulator under the cell plate and a diffused layer in the major surface of the substrate under the cell plate. The transistor 2 in each memory cell includes, as a source electrode, a source diffused layer in the major surface of the substrate; as a drain electrode, a drain diffused layer, which is part of the diffused layer of the capacitor 3; and a gate electrode, formed on the major surface of the substrate through a gate insulator, which is part of the word line 5.
In the above-constructed memory cell, when the level of the selected word line 5 is high and the selected transistor 2 is in a conductive state during reading, the information stored in the capacitor 3 is transferred to the selected bit line 4a or 4b. When the level of the word line 5 is low and the transistor 2 is in a non-conductive state during writing the information stored in the capacitor 3 is retained.
The above described memory cell has the following problems. First of all, current leaks readily along the inside isolating face of the isolating region 6 located along the transistor 2 as shown in the direction of an arrow in FIG. 2, even when the transistor 2 is in a non-conductive state. This current leakage occurs because the direction of current flow from the bit line 4a, 4b to the capacitor is parallel to the inside isolating face of the isolating region 6. As a result, the information stored in the capacitor may be lost.
A second disadvantage arises because according to the above-described construction, a high density implanted layer for isolating adjacent memory cells from each other is diffused as far as the inside isolating face of the isolating region 6. As a result, the channel width of the transistor 2 is narrowed by the high density implanted layer, causing variability in the threshold voltage.